This invention relates generally to calibrating and/or deskewing communications channels. Communications channels are used in any number of devices or systems, and in many such applications it may be advantageous to calibrate or deskew the communications channels. One nonlimiting example of the use of communications channels is a test system, such as for testing electronic devices.
FIG. 1 illustrates a simplified block diagram of an exemplary test system 100 for testing electronic devices, such as semiconductor devices. For example, the test system 100 of FIG. 1 may test the dies of an unsingulated wafer, singulated dies (packaged or unpackaged), or multi-chip modules. Such a system 100 may be configured to test other types of electronic devices, such as printed circuit boards, as well. As shown, the system 100 may include a tester 102, communications connection 104, probe head 107, and a probe card 108 for communicating test signals between the tester 102 and the electronic device under test (“DUT”) 112. The test system 100 also may include a housing 106 with a moveable chuck 114 for supporting and moving the DUT 112. Probes 110 of the probe card make contact with the DUT 112 and thereby form electrical connections with the DUT.
The communications connection 104 (e.g., a coaxial cable, fiber optic, wireless link, etc.), test head 107, and probe card 110 form multiple communications channels (not shown in FIG. 1) between the tester 102 and terminals (not shown in FIG. 1) of the DUT 112. The tester 102 generates test data, which is driven through those communications channels (not shown in FIG. 1), to the terminals (not shown in FIG. 1) of the DUT 112. Response data generated by the DUT 112 travels in the reverse direction through other such communications channels (not shown in FIG. 1) back to the tester 102. In some test systems, the same communications channel is used for both test data and response data.
FIG. 2 illustrates a simplified block diagram of an exemplary tester 102 configured to test a DUT 112 that has two input terminals 220 and 222 and one output terminal 234. For example, DUT 112 may be a small memory with four one-bit storage cells. In response to a two-bit address input into input terminals 220 and 222, internal circuitry (not shown) in DUT 112 outputs through output terminal 234 the one-bit datum stored in the storage cell that corresponds to the address. (Of course, a memory DUT would typically have many more address inputs and many more data outputs and other inputs and outputs. The DUT 112 shown in FIG. 2 is simplified for purposes of illustration and discussion.)
As shown in FIG. 2, tester 102 includes a test data generator 202 that generates test patterns to be input into the input terminals 220 and 222 of DUT 112. In this example, each test pattern consists of two bits. Test data generator 202 outputs 204 the test patterns to a timing controller 206, which outputs 208, 210 each bit in the test pattern to drivers 212, 214. Drivers 212, 214 drive the test pattern through drive channels 216, 218 to input terminals 220, 222. As discussed above, although not shown in FIG. 2, channels 216, 218 may include paths through such things as a communications link (e.g., 104 in FIG. 1), a test head (e.g., 107 in FIG. 1), and a probe card (e.g., 108 in FIG. 1). Compare channel 232 (which may include the same paths as drive channels 216, 218) carries to the tester 102 the output generated by DUT 112 in response to the test pattern. (Herein, a communications channel (e.g., 216) for carrying test data from the tester 102 to the DUT 112 is referred to as a “drive channel” and a communications channel (e.g., 232) for carrying response data from the DUT 112 to the tester 102 is referred to as a “compare channel.” It should be noted that, in many testers, a channel may be selectively set to function as a drive channel or a compare channel or to function as both a drive channel and a compare channel.) Comparator 228 compares the output generated by the DUT 112 to the expected response, which is input 226 to comparator 228. Results acquisition/analyzer 230 receives the results of the comparison and may also analyze the comparison to determine whether DUT 112 responded correctly to the test pattern. Test data generator 202, along with the test pattern, may also generate the expected response, and also output 226 the expected response to the timing controller 206. Timing controller 206 outputs 226 the expected response along with a compare signal 224 that activates comparator 228 at a time when the response data generated by the DUT is expected to arrive at the comparator 228 on channel 232.
As might be expected, timing of signals in the system shown in FIG. 2 is typically important. For example, it is typically important for the bits of the test pattern to arrive at the input terminals 220, 222 of DUT 112 at the same time or within a specified time difference. As another example, it is typically important for the expected response 226 and the compare signal 224 to be activated at the same time as or within a specified time difference of the arrival from DUT 112 of response data at comparator 228 on compare channel 232. In many applications, differences in the propagation delay of a signal through the drive channels 216, 218 and compare channel 232 must be compensated for.
FIG. 3 shows an exemplary timing chart for signals in the system of FIG. 2. In the example shown in FIG. 3, all timing is relative to the rising edge of a master clock 302, which may be generated in timing controller 206 or elsewhere in tester 102. Of course, something other than the rising edge of a master clock may be used as a timing reference. As shown in FIG. 3, timing generator 206 delays the output 208, 210 (see FIG. 2) of each bit of a test pattern by different offsets 314, 316 so that the bits in the test pattern arrive at the input terminals 220, 222 of DUT 112 (see FIG. 2) at the same or approximately the same time despite differences in the propagation delays through drive channels 216, 218. In the example shown in FIG. 3, the bit (represented in FIG. 3 by pulse 304) input 208 to driver 212 is delayed by a time offset 314, and the bit (represented in FIG. 3 by pulse 306) input 210 to driver 214 is delayed by a time offset 316. As also shown in FIG. 3, this causes the bits to arrive at the input terminals 220, 222 of DUT 112 at the same or approximately the same time. (The bit input 208 to driver 212 and driven down drive channel 216 is represented as it arrives at input terminal 220 by pulse 304′ in FIG. 3; similarly, the bit input 210 to driver 214 and driven down drive channel 218 is represented as it arrives at input terminal 222 by pulse 306′ in FIG. 3.) Of course, offset 314 may be zero. Offset 318 in FIG. 3 represents the delay from the timing reference (in this example, the rising edge of master clock pulse 302) to the presentation of expected response data 226 and the compare signal 224 to the comparator 228 (see FIG. 2). (In FIG. 3, the expected response data is represented by pulse 308, and the compare signal is represented by pulse 312. As shown in FIG. 3, offset 318 is set so that the compare signal (pulse 312 in FIG. 3) coincides with the arrival at comparator 228 of response data from DUT 112 on compare channel 232.
Offsets 314, 316, and 318 may be stored in a memory table or array (not shown) in timing controller 206. Moreover, each offset 314, 316, and 318 may comprise multiple parts. For example, a test system, such as test system 100 in FIG. 1, may be initially calibrated without a probe card 108, and later deskewed with a probe card 108. Each offset 314, 316, and 318 may therefore comprise a calibration delay representing the delay through a part of a corresponding drive or compare channel from the tester 102 to the interface (not shown) between the test head 107 and the probe card 108 and a deskew delay representing the delay through the probe card. The term “calibrate” is often used to refer to setting timing delays or timing offsets to make the propagation delays to the interface between the probe head 107 and the probe card 108 equal, and the term “deskew” is often used to refer to setting an addition timing delay or offset to compensate for differences in propagation delays through the probe card. In this application, however, the terms “calibrate” and “deskew” are used broadly and synonymously to include the determination and/or setting of any timing delay or offset, whether related to part or all of a channel. The terms “time delay” and “offset” are also used broadly and synonymously.
There is a need for improved methods and apparatuses for determining calibration and/or deskew offsets.